Reference is made to FIGS. 1A-1E which generally illustrate the process steps associated with the sidewall image transfer (SIT) manufacturing process (also referred to as sidewall image patterning (SIP) by those skilled in the art). Sidewall image processing is a technique which permits the production of sub-resolution features for integrated circuits. The process starts in FIG. 1A with a substrate 10. The substrate 10 may comprise any substrate as known to those skilled in the art and may include many layers, structures and components (not shown). The substrate 10 has a planar top surface 12 which may, for example, be obtained by chemical mechanical polishing (CMP) of an upper-most layer of the substrate 10. A patterned resist image 14 is then formed on the top surface 12 of the substrate 10 (FIG. 1B). The pitch 13 of the image 14 is constrained by the lithographic limits of the patterning process. A conformal coating 16 is then formed over the resist image 14 (FIG. 1C). The coating 16 may, for example, comprise an oxide material such as silicon dioxide. A highly directional etch is then used to remove the planar areas of the coating 16 so as to leave sidewalls (also referred to as collars) 18 of the coating material on either side of the features 20 of the patterned resist image 14 (FIG. 1D). Another etch is then performed to remove the features 20 (FIG. 1E). As can be seen, the advantage of this process is the ability to form very narrow lines with well-controlled widths, and thus produce a feature pitch 15 which is smaller than the pitch 13 of the lithographic process. Using an additional lithographic mask and etch, the structure shown in FIG. 1E may be trimmed to remove unwanted closed loops formed by the encircling pattern of the sidewalls 18 and thus form lines. The resulting line width is limited by the verticality of the original resist image features 20, the accuracy of the conformal coating 16 and the directionality of the coating etch. In a preferred implementation, the parameters of the process are controlled so that the pitch 15 of the sidewall pattern (FIG. 1E) is one-half the pitch 15 of the resist pattern (FIG. 1B).
As technology nodes continue to scale down beyond 20 nm, the requirement for obtaining different resistivity interconnections with high integration density has become extremely challenging. A current solution known to those skilled in the art is to use a different trench critical dimension (CD) at the same metallization level in order to form different resistivity interconnection lines. This solution has a drawback in that it requires a large integration area.
There is accordingly a need in the art for an improved method for forming interconnection lines with different resistivities while maintaining a constant line pitch. It would be preferred if the process did not introduce or require the use of an additional hard mask and etch.